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• W1570626776 abstract "An approach is presented for hierarchical, trace-theoretic verification of speed-independent circuits based on Petri net unfolding. The purpose is to avoid the explosion of states that results from interleaving of concurrent transitions. The trace structures of the circuit components are represented by Petri nets. Conformance between implementation and specification is tested by composing the implementation with the mirror of the specification, unfolding the resulting product net into an occurrence net, and testing this net for failures. The latter problem is shown to be NP-complete, however a practical branch-and-bound algorithm is presented. In two examples of scalable asynchronous control circuits, the unfolding size is found to grow linearly with the circuit size, while the number of states grows exponentially. In one case, the unfolding method succeeds in verifying large configurations while BDD-based traversal techniques do not." @default.
• W1570626776 created "2016-06-24" @default.
• W1570626776 creator A5047507250 @default.
• W1570626776 date "1995-01-01" @default.
• W1570626776 modified "2023-10-17" @default.
• W1570626776 title "Trace theoretic verification of asynchronous circuits using unfoldings" @default.
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• W1570626776 doi "https://doi.org/10.1007/3-540-60045-0_50" @default.
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