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- W1570682605 abstract "A 96 dB SFDR 50 MS/s pipeline A/D converter has been designed in a 0.25 /spl mu/m CMOS process. An improved sample-and-hold and subtractive dither-continuous gain correction (SD-CGC) digital calibration are used to increase linearity. Prototype measurements show that the SNDR increases from 49 dB to 75 dB and the SFDR increases from 62 dB to 96 dB using the technique." @default.
- W1570682605 created "2016-06-24" @default.
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- W1570682605 date "2004-01-01" @default.
- W1570682605 modified "2023-09-26" @default.
- W1570682605 title "A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter" @default.
- W1570682605 cites W2135245081 @default.
- W1570682605 doi "https://doi.org/10.1109/isscc.2004.1332791" @default.
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