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• W1570690206 abstract "The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law during more than 40 years. Today the traditional scaling has reached limits when physical phenomena inherent to the nanoscale generate as many challenges and issues as the gain in performance compared to previous device generation. This work proposes another alternative to overcome the difficulty of traditional scaling and still continue to increase the integration density and with improved device performances: the vertical stacking of devices or the completion of the planar integration with an in-volume, vertical integration of multiple channels and other structures. In contrast with many other works, we investigated stacking of channel on bulk silicon substrates which will avoid the higher costs of engineered substrates like SOI. This thesis reports on the development of strategies to fabricate advanced multilevel 3D structures in bulk silicon, and their integration as stacked transistor channels. We propose some credible alternatives for the design, fabrication and characterization of a Field Effect Transistor exploiting vertically stacked channels. We investigate two main technologies: (i) silicon transformation during a high temperature annealing in hydrogen ambient, and, (ii) profile engineered trenches. We propose several design and process optimization to be able to fabricate stacked silicon structures (membranes, nanowires, Fins) that could be used as suspended transistor channels. Two original fabrication processes are presented, enabling the manufacturing of bulk silicon transistors with a matrix of stacked channels. We successfully validate the fabrication process of two level suspended Fin channel transistor. Double-stacks of nanowires stacks (promoting a new concept of stacking the stacks) are also demonstrated morphologically. Some of the fabricated structures are electrically characterized, demonstrating basic functionally of a MOSFET but also some difficult control of parasitic transistor effect. We have tried to eliminate such effects by a special design of the source and drain pads in a second integration process. The transfer, Id-Vg, and output, Id-Vd, characteristics of fabricated devices always show a transistor behavior and the extracted mobility values for n-type transistors tend to confirm that the conduction in the suspended channels dominates over the sidewall or bottom parasitic transistor. However, the presence of a parasitic transistor remains important and its elimination needs further efforts. The demonstrated 3D silicon structures in this work show the possibility to sculpture and integrate stacked channels in bulk silicon for making MOSFETs with multiple suspended channels, potentially with independently control of these channels. The morphological work carried out can also find novel applications in other silicon applications areas, like photonics, micro fluidics and Micro-Electro-Mechanical-Systems." @default.
• W1570690206 created "2016-06-24" @default.
• W1570690206 creator A5070442279 @default.
• W1570690206 date "2011-01-01" @default.
• W1570690206 modified "2023-09-23" @default.
• W1570690206 title "In-IC Strategies for 3D Devices in Bulk Silicon" @default.
• W1570690206 doi "https://doi.org/10.5075/epfl-thesis-4864" @default.
• W1570690206 hasPublicationYear "2011" @default.
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