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- W157274830 abstract "This chapter provides an overview of the dynamic ring architecture. It presents the architecture for the emulation of multi-layered perceptrons with backpropagation learning. Each processor contains three communication ports and is also connected to a common bus. At each particular time slice, a layer is emulated and only two ports are activated simultaneously—one for the input and the other for the output. The bus serves both for fetching instructions and exchanging data with the array controller and host. This structure has several advantages, such as: (1) it is modular, (2) easily expandable, and (3) efficient in the use of computing resources. Two concepts embodied in the architecture are worth mentioning: (1) virtual neurons—wherein each processor may actually emulate several physical neurons. (2) Virtual layers—wherein each processor and the whole architecture emulate a particular neural network layer depending on the time-slice considered. Because of the virtual layer capability of the architecture, it is clear that a two-dimensional structure is mapped to a one-dimensional architecture." @default.
- W157274830 created "2016-06-24" @default.
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- W157274830 date "1992-01-01" @default.
- W157274830 modified "2023-10-17" @default.
- W157274830 title "The Dynamic Ring Architecture**This research is supported in part by Semiconductores Corp., author J.M. Moreno is an FI scholar under the Generalitat de Catalunya's Educ. Dept." @default.
- W157274830 cites W1534058569 @default.
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- W157274830 doi "https://doi.org/10.1016/b978-0-444-89488-5.50131-7" @default.
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