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- W157319038 abstract "To deal with the increasing design complex- ity of integrated systems reuse of intellectual property (IP) blocks is promoted. A system architecture then becomes a composition of a heterogeneous set of such IP blocks to- gether with a network that interconnects these blocks. The main challenge of system design therefore shifts from com- putation (IP blocks) to communication and storage (inter- connect and memories). This means that applications be- come dynamic compositions of IP blocks which requires that the network is scalable (in the number of attached IP blocks), programmable and behaves predictably under the traffic offered by those blocks. As the feature size decreases the relative cost of wires in- creases. We therefore search for an interconnect network that efficiently uses wires through sharing by introducing routers. For a flexible and efficient solution at least two traffic classes must be support by the network, viz., guaranteed- throughput (GT) and best-effort (BE). For GT traffic com- munication channels are set up to transport data between IP blocks (possibly via memory). Best-effort traffic is never lost, but no latency or through-put guarantees are given. We also address the conflicting requirements of GT and BE traffic (1). Our router is packet-switched and uses input-queuing with an efficient packet/flit scheduling (2) for BE traffic, whereas efficient time division multiplexing scheme is used is used for GT traffic. The focus of this paper is on the derivation of a cost- effective router and network suitable for on-chip integra- tion." @default.
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- W157319038 date "2001-01-01" @default.
- W157319038 modified "2023-10-01" @default.
- W157319038 title "A Router Architecture for Networks on Silicon" @default.
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