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- W1575606279 abstract "We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system." @default.
- W1575606279 created "2016-06-24" @default.
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- W1575606279 date "2002-11-22" @default.
- W1575606279 modified "2023-10-06" @default.
- W1575606279 title "Design methodology for chip-on-chip applications" @default.
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- W1575606279 doi "https://doi.org/10.1109/epep.1997.634024" @default.
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