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- W1575612116 abstract "An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation, the Xilinx Artix 7 (xc7a100tl-csg324C) FPGA device was used." @default.
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- W1575612116 date "2015-06-01" @default.
- W1575612116 modified "2023-09-23" @default.
- W1575612116 title "A compact design of SEED block cipher" @default.
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- W1575612116 doi "https://doi.org/10.1109/meco.2015.7181881" @default.
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