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- W1576821041 abstract "In this study, we discuss communication aspects concerning a segmented bus platform. Placed somewhere midway between the classical system bus and the network on chip approaches, the segmented bus architecture provides certain performance improvements in comparison with the first, while employing a much simpler communication structure and algorithm than those thought for the second. Our implementation strategy targets an FPGA technology. The result comes as a parameterized communication scheme for system on chip designers." @default.
- W1576821041 created "2016-06-24" @default.
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- W1576821041 date "2004-12-23" @default.
- W1576821041 modified "2023-09-27" @default.
- W1576821041 title "Communication on a segmented bus platform" @default.
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- W1576821041 doi "https://doi.org/10.1109/socc.2004.1362409" @default.
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