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• W1579367023 startingPage "124" @default.
• W1579367023 abstract "We describe an FPGA accelerator for the Kannan–Fincke–Pohst enumeration algorithm (KFP) solving the Shortest Lattice Vector Problem (SVP). This is the first FPGA implementation of KFP specifically targeting cryptographically relevant dimensions. In order to optimize this implementation, we theoretically and experimentally study several facets of KFP, including its efficient parallelization and its underlying arithmetic. Our FPGA accelerator can be used for both solving stand-alone instances of SVP (within a hybrid CPU–FPGA compound) or myriads of smaller dimensional SVP instances arising in a BKZ-type algorithm. For devices of comparable costs, our FPGA implementation is faster than a multi-core CPU implementation by a factor around 2.12." @default.
• W1579367023 created "2016-06-24" @default.
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• W1579367023 date "2010-01-01" @default.
• W1579367023 modified "2023-10-18" @default.
• W1579367023 title "Accelerating Lattice Reduction with FPGAs" @default.
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• W1579367023 doi "https://doi.org/10.1007/978-3-642-14712-8_8" @default.
• W1579367023 hasPublicationYear "2010" @default.
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