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- W1579412944 abstract "Recently-described CMOS serial links operate at multiple gigabits/s signaling rates over several meters of cable. However, these previous links require large amounts of power and chip area, making them unsuitable for applications requiring hundreds of I/Os per chip. The best previously-published power and area above 4 Gb/s in CMOS are 310 mW and 0.6 mm/sup 2/. Integration of a hundred of these I/Os would burn more than 30 W of power and consume 60 mm/sup 2/ of chip area. The 4 Gb/s transceiver described here dissipates only 90 mW and requires less than 0.1 mm/sup 2/ chip area. This transceiver achieves low-power and low area using an input-multiplexed transmitter architecture, a regulated CMOS inverter-based delay-locked loop (DLL), and receiver offset calibration." @default.
- W1579412944 created "2016-06-24" @default.
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- W1579412944 date "2002-11-07" @default.
- W1579412944 modified "2023-09-26" @default.
- W1579412944 title "A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation" @default.
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- W1579412944 doi "https://doi.org/10.1109/isscc.2000.839772" @default.
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