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- W1579964948 abstract "Caches are known to consume up to half of all system power in embedded processors. Co-optimizing performance and power consumption of the cache subsystem is therefore an important step in the design of embedded systems, especially those employing application specific instruction processors. One of the main difficulty in such attempts is that cache behaviors are application as well as cache-structure specific. The two general approaches to tackling this problem is to either use exhaustive simulation or analytical modeling. The former is too time-consuming while the latter often lacks the required accuracy. In this paper, we introduce a novel third approach. We propose an analytical cache model that interpolates data from runs with direct mapped and fully associative caches so that the entire parameter space involving all set-associativity is spanned. Validation against full trace-driven simulations shows that our model has a very high degree of fidelity, but requires significantly less simulation time than exhaustive simulation. Furthermore, the model works for instruction, data or unified caches. Finally, we show how the model can be coupled with a power model for caches so that one can very quickly decide on pareto-optimal performance-power design points for rapid design space exploration." @default.
- W1579964948 created "2016-06-24" @default.
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- W1579964948 date "2005-01-01" @default.
- W1579964948 modified "2023-09-27" @default.
- W1579964948 title "An Interpolative Analytical Cache Model with Application to Performance-Power Design Space Exploration" @default.
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