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• W1580024056 abstract "Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry." @default.
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• W1580024056 date "2015-09-01" @default.
• W1580024056 modified "2023-09-30" @default.
• W1580024056 title "Best Practices for Compact Modeling in Verilog-A" @default.
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• W1580024056 doi "https://doi.org/10.1109/jeds.2015.2455342" @default.
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