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- W1585256428 abstract "The impact of spacer design on the electrostatic integrity (EI) and performance of Ultra-Thin-Body (UTB) InGaAs-OI MOSFETs with various high-k dielectrics are analyzed. With fixed EOT and Ioff, performance and EI degrade as gate dielectric constant (k) increases. Compared with nitride spacer, UTB InGaAs-OI MOSFET with vacuum spacer can mitigate the EI and performance degradations due to thicker physical layer of high-k dielectric. UTB InGaAs-OI MOSFET with high-k dielectric (k ≥ 18) and vacuum spacer shows larger Ion, smaller DIBL and subthreshold swing than that with nitride spacer. With fixed EOT, using gate-to-source/drain underlap can suppress the performance degradation as gate dielectric constant increases. For UTB InGaAs-OI MOSFET with underlap design, using nitride spacer may improve its gate control of channel potential and show better performance than vacuum spacer." @default.
- W1585256428 created "2016-06-24" @default.
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- W1585256428 date "2015-04-01" @default.
- W1585256428 modified "2023-09-22" @default.
- W1585256428 title "Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design" @default.
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- W1585256428 doi "https://doi.org/10.1109/vlsi-tsa.2015.7117568" @default.
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