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• W1586842010 abstract "This paper describes a 20-lane 62.5 Gb/s SerDes designed as an interface between the 40G, or quad 10G Optics, and a downstream framer device. Transmit and receive clocks are derived from an LC-based PLL with a wideband RMS jitter below 2.5 ps. Timing recovery uses a 2/sup nd/ order loop and includes over-sampled /spl Delta//spl Sigma/ techniques to achieve both narrowband filtering and excellent jitter tolerance. To support backplane applications, line driver and receiver incorporate preemphasis and equalization respectively." @default.
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• W1586842010 date "2004-02-03" @default.
• W1586842010 modified "2023-09-26" @default.
• W1586842010 title "A 62.5 Gb/s multi-standard SerDes IC" @default.
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• W1586842010 doi "https://doi.org/10.1109/cicc.2003.1249466" @default.
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