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- W1590765702 abstract "This paper details the implementation of a highly pipelined 2.5 Gbit/s point-to-point-protocol packet processor (P/sup 5/) aimed at the latest system-on-a-programmable-chip (SoPC) technology. Throughput rates beyond 2.5 Gbit/s based on FPGA technology could be achieved by designing a new highly pipelined and parallel processing architecture for frames and datagrams. A novel pipelined data sorting mechanism with an extremely low resynchronization buffer and backpressure scheme are introduced to keep the data memory requirements as low as possible for embedded on-chip applications." @default.
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- W1590765702 date "2004-03-22" @default.
- W1590765702 modified "2023-09-26" @default.
- W1590765702 title "A programmable and highly pipelined PPP architecture for Gigabit IP over SDH/SONET" @default.
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- W1590765702 doi "https://doi.org/10.1109/ipdps.2003.1213331" @default.
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