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- W1591295384 abstract "In this paper, a new architecture for cyclic algorithmic DA converters will be proposed. The upper bound for the maximum number of converted bits will be expressed in the mismatch error of the factor 1/2. It turns out that the number of relevant bits is twice the number achieved in the conventional technique under the same assumed mismatch error, without raising the conversion time above n-times a single bit conversion. An implementation in switched-current technique is treated." @default.
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- W1591295384 date "2002-11-19" @default.
- W1591295384 modified "2023-09-27" @default.
- W1591295384 title "A new architecture for a cyclic algorithmic DA converter" @default.
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- W1591295384 doi "https://doi.org/10.1109/iscas.1995.519889" @default.
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