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- W1594881912 abstract "We improve the performance of main-memory binary search trees (including AVL and red-black trees) by applying cache-sensitive and cache-oblivious memory layouts. We relocate tree nodes in memory according to a multi-level cache hierarchy, also considering the conflict misses produced by set-associative caches. Moreover, we present a method to improve one-level cache-sensitivity without increasing the time complexity of rebalancing. The empirical performance of our cache-sensitive binary trees is comparable to cache-sensitive B-trees. We also use the multi-level layout to improve the performance of cache-sensitive B-trees." @default.
- W1594881912 created "2016-06-24" @default.
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- W1594881912 date "2008-07-21" @default.
- W1594881912 modified "2023-09-25" @default.
- W1594881912 title "Cache-sensitive Memory Layout for Binary Trees" @default.
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- W1594881912 doi "https://doi.org/10.1007/978-0-387-09680-3_17" @default.
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