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- W1598045274 abstract "In this paper, we focus on the design of digital baseband inner receiver for Power Line Communication (PLC) system based on IEEE P1901 specification. The baseband receiver is composed of digital received filter, synchronization, fast Fourier transform (FFT), channel estimation/equalization and timing frequency offset (TFO) synchronization. The baseband receiver provides the throughput rate of 170 Mbps with 1024-QAM constellation. The chip is designed with 90 nm CMOS process. The core area is 2.071×2.071 mm2 with the power consumption of 89.9 mW at the supply voltage of 1.0 V." @default.
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- W1598045274 date "2015-06-01" @default.
- W1598045274 modified "2023-09-24" @default.
- W1598045274 title "Design of digital baseband inner receiver for PLC system based on IEEE P1901 specification" @default.
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- W1598045274 doi "https://doi.org/10.1109/icce-tw.2015.7216860" @default.
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