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- W1599366940 abstract "The access time, latency, and yield of embedded caches limit present generation processors to incorporate approximately 128 kB of memory. This 1.8 ns access time four-way-set-associative on-chip 1 MB data cache (D-cache) and 1.6 ns access time four-way-set-associative on-chip 0.5 MB instruction cache (I-cache) allow single-cycle access with up to three stores or loads executed every cycle. The caches communicate with the CPU over two 64 b data busses and a 128 b instruction bus running at the processor clock frequency of 500 MHz for 16 GB/s total effective bandwidth." @default.
- W1599366940 created "2016-06-24" @default.
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- W1599366940 date "2003-01-20" @default.
- W1599366940 modified "2023-09-25" @default.
- W1599366940 title "A 500 MHz 1.5 MB cache with on-chip CPU" @default.
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- W1599366940 doi "https://doi.org/10.1109/isscc.1999.759189" @default.
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