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- W1602676648 abstract "This paper presents an improved frequency compensation technique for low power and low voltage CMOS operational amplifier. The op amp designed for a high speed high resolution pipeline ADC is a two-stage with folded-cascode as the first stage and uses this improved compensation technique to achieve closed loop bandwidth of 350 MHz while driving a 2K resistor load and a 3.5 pF capacitive load consuming much lower power when compared to the conventional Miller compensation technique or cascode compensation technique. The op amp was designed in a 0.15-/spl mu/m CMOS technology and achieves a THD of 70 dB for a 30 MHz signal and consumes a total power of 4 mW of a 1.35 V supply." @default.
- W1602676648 created "2016-06-24" @default.
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- W1602676648 date "2004-09-07" @default.
- W1602676648 modified "2023-09-26" @default.
- W1602676648 title "An improved frequency compensation techinique for low power, low voltage CMOS amplifiers [techinique read technique]" @default.
- W1602676648 cites W1972150182 @default.
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- W1602676648 doi "https://doi.org/10.1109/iscas.2004.1328240" @default.
- W1602676648 hasPublicationYear "2004" @default.
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