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• W1603436218 abstract "We present a new collector construction for high-speed SiGe:C HBTs that substantially reduces the parasitic base-collector capacitance by selectively underetching of the collector region. The impact of the collector module on RF performance is demonstrated in separate bipolar processes for npn and pnp devices. A minimum gate delay of 3.2ps was achieved for CML ring oscillators with npn transistors featuring f/sub T//f/sub max/ values of 300GHz/250GHz at BV/sub CEO/ = 1.8V. For pnp devices with f/sub T//f/sub max/ values of 135GHz/140GHz at BV/sub CEO/ = 2.5V a gate delay of 5.9ps is demonstrated. Further vertical scaling of the doping profiles increases f/sub T/ to 380GHz at BV/sub CEO/=1.5V for npn's and 155GHz at BV/sub CEO/ = 2.3V for pnp's, but ring oscillator speed and f/sub max/ degraded." @default.
• W1603436218 created "2016-06-24" @default.
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• W1603436218 date "2005-04-19" @default.
• W1603436218 modified "2023-09-26" @default.
• W1603436218 title "A low-parasitic collector construction for high-speed SiGe:C HBTs" @default.
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• W1603436218 doi "https://doi.org/10.1109/iedm.2004.1419123" @default.
• W1603436218 hasPublicationYear "2005" @default.
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