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- W1607618404 abstract "Wave pipelining improves the throughput of a circuit by exploiting the delays of combinational elements, rather than register clocks, for synchronization. We proposed a new design approach for high speed circuits which combines the conventional register-based pipelining with wave-pipelining. Our approach, called HyPipe, aims to take the advantages of both pipelining methods. We applied our method to 1-bit and 2-bit adder cells, which can be used as building blocks for larger size adders and multipliers. Our experimental results show that the 1-bit adder achieves the throughput of 2.4 billion additions/second and the 2-bit adder achieves 2.2 billion additions/second for TSMC 0.25 /spl mu/m technology. Furthermore, they have potential for even higher throughputs provided registers are able to operate faster." @default.
- W1607618404 created "2016-06-24" @default.
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- W1607618404 date "2003-08-27" @default.
- W1607618404 modified "2023-09-25" @default.
- W1607618404 title "HyPipe: a new approach for high speed circuit design" @default.
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- W1607618404 doi "https://doi.org/10.1109/asic.2002.1158057" @default.
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