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• W1607803548 abstract "The radio-frequency (RF) performance of a 0.18-/spl mu/m CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies (f/sub T/ and f/sub max/), the minimum noise figure (F/sub min/) and associated power gain (G/sub a/), and the 1/f noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the RF performance without any technology process modifications. Changing to N/sub 2/O gate dielectrics is shown to greatly reduce the 1/f noise without sacrificing the AC performance. The power amplifier characteristics of CMOS at low power levels are also discussed." @default.
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• W1607803548 date "2000-04-01" @default.
• W1607803548 modified "2023-09-27" @default.
• W1607803548 title "RF potential of a 0.18-μm CMOS logic device technology" @default.
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• W1607803548 doi "https://doi.org/10.1109/16.831006" @default.
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