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- W1616047807 abstract "The authors present two methods for optimizing the topology of given power/ground networks on VLSI chips. The cycle-reduction-method removes cycles and root paths (paths between two pads) in a general power/ground graph. The node-reduction-method removes branching nodes (nodes incident to more than two branches) in a power/ground tree. Both methods yield a reduction of the power/ground routing area and do not degrade the reliability of the power/ground network. Small examples to explain the procedures are included and experimental results for benchmark circuits are presented. >" @default.
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- W1616047807 date "2003-01-02" @default.
- W1616047807 modified "2023-09-26" @default.
- W1616047807 title "Topology optimization techniques for power/ground networks in VLSI" @default.
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- W1616047807 doi "https://doi.org/10.1109/eurdac.1992.246218" @default.
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