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• W1638823770 abstract "Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced timing errors in NoCs and preserve error-free communication throughout the network. DrNoC employs frequency downscaling and a pipeline error-recovery mechanism to reclaim corrupted flits in the router. Compared to the recently proposed NSFTR fault-tolerant technique, DrNoC offers a 27% improvement in energy-delay efficiency." @default.
• W1638823770 created "2016-06-24" @default.
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• W1638823770 date "2015-07-01" @default.
• W1638823770 modified "2023-09-26" @default.
• W1638823770 title "Tackling voltage emergencies in NoC through timing error resilience" @default.
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• W1638823770 doi "https://doi.org/10.1109/islped.2015.7273498" @default.
• W1638823770 hasPublicationYear "2015" @default.
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