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• W1643989195 startingPage "2476" @default.
• W1643989195 abstract "Designing four-stage operational transconductance amplifiers (OTAs) is often considered a challenging task mainly because of the required non trivial frequency compensation procedure. In this study, starting from the simplest architecture (a differential stage cascaded by three common source stages) a high-performance OTA is demonstrated, outperforming all the (few) previous implementations. Thanks to the frequency compensation scheme and to the adoption of a slew-rate enhancer section, the solution is able to drive large capacitive loads as high as 1 nF, rivaling in terms of bandwidth and speed even with three-stage counterparts, traditionally credited to be better because of the less number of high-impedance nodes. The solution, fabricated in a 0.35-μm technology, occupies 0.014-mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> with DC consumption of 170 μW. It also achieves nearly 3-MHz gain bandwidth product while driving the 1-nF load with less than 0.5-μs 1% settling time." @default.
• W1643989195 created "2016-06-24" @default.
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• W1643989195 date "2015-10-01" @default.
• W1643989195 modified "2023-09-25" @default.
• W1643989195 title "High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads" @default.
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• W1643989195 doi "https://doi.org/10.1109/tcsi.2015.2476298" @default.
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