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- W1644106052 abstract "Multiprocessor (MP-SoC) platforms are emerging as the latest trend in SoC design. These MP-SoCs consist of a large number of IP blocks in the form of functionally heterogeneous embedded processors. In this design paradigm, IP blocks need to be integrated using a structured interconnect template, for example, according to high-performance parallel computing architectures. A formal evaluation process is required before adopting a specific parallel architecture to SoC domain. Here, we propose an evaluation methodology based on performance metrics that include latency, throughput and silicon area requirements. As a case study, we present the results of such an evaluation for two MP-SoC interconnect topologies, i.e., the mesh and the butterfly fat-tree (BFT). This evaluation methodology can be extended to any other SoC interconnect topology without loss of generality." @default.
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- W1644106052 date "2004-07-19" @default.
- W1644106052 modified "2023-09-26" @default.
- W1644106052 title "Evaluation of MP-SoC interconnect architectures: a case study" @default.
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- W1644106052 doi "https://doi.org/10.1109/iwsoc.2004.38" @default.
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