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- W1646161576 abstract "Multi-Processor System-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection architectures determining various trade-offs between cost and performance. An automated methodology for optimizing FPGA-based MPSoC interconnect architectures is summarized in this poster paper. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints. The resulting architecture improves the level of communication parallelism while containing area and power costs." @default.
- W1646161576 created "2016-06-24" @default.
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- W1646161576 date "2015-09-01" @default.
- W1646161576 modified "2023-09-25" @default.
- W1646161576 title "Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip" @default.
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- W1646161576 doi "https://doi.org/10.1109/fpl.2015.7293989" @default.
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