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- W1651154206 abstract "In this paper, an implementation of both interpolation and synchronization modules designed for RF receiver using power-gated ADC (PG-ADC) is presented. These modules allow lower bit error rates when demodulating non-uniformly sampled minimum-shift keying (MSK) signal. The proposed architectures are synthesized using CMOS 90 nm technology and are shown to have small occupied area (≈0.05 mm2) and low power consumption (tens to hundreds of µW). The results are detailed for several input data rates and interpolation factors." @default.
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- W1651154206 date "2015-08-01" @default.
- W1651154206 modified "2023-09-26" @default.
- W1651154206 title "Digital cubic interpolation and synchronization for RF receiver using power-gated ADC" @default.
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- W1651154206 doi "https://doi.org/10.1109/mwscas.2015.7282055" @default.
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