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- W1652802933 abstract "A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL_PT) and its counterpart in conventional CMOS logic, was carried out in a 0.13mum PD (partially depleted) SOI CMOS for a supply voltage of 1.2V and a threshold voltage of 0.28V. Moreover, MTCMOS (multi-threshold) circuit technique was applied on the proposed full-adder to achieve a trade-off between Ultra-Low power and high performance design. Design with DTMOS (dynamic threshold) devices was also investigated with two threshold voltage values (0.28V and 0.4V) and V-dd = 0.6V." @default.
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- W1652802933 date "2004-01-01" @default.
- W1652802933 modified "2023-09-25" @default.
- W1652802933 title "Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell" @default.
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- W1652802933 doi "https://doi.org/10.1007/978-3-540-30205-6_21" @default.
- W1652802933 hasPublicationYear "2004" @default.
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