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• W165697058 abstract "The miniaturization race in the hardware industry aiming at continuous increasingof transistor density on a die does not bring respective application performanceimprovements any more. One of the most promising alternatives is toexploit a heterogeneous nature of common applications in hardware. Supported byreconfigurable computation, which has already proved its efficiency in acceleratingdata intensive applications, this concept promises a breakthrough in contemporarytechnology development.Memory organization in such heterogeneous reconfigurable architectures becomesvery critical. Two primary aspects introduce a sophisticated trade-off. Onthe one hand, a memory subsystem should provide well organized distributed datastructure and guarantee the required data bandwidth. On the other hand, it shouldhide the heterogeneous hardware structure from the end-user, in order to supportfeasible high-level programmability of the system.This thesis work explores the heterogeneous reconfigurable hardware architecturesand presents possible solutions to cope the problem of memory organizationand data structure. By the example of the MORPHEUS heterogeneous platform,the discussion follows the complete design cycle, starting from decision makingand justification, until hardware realization. Particular emphasis is made on themethods to support high system performance, meet application requirements, andprovide a user-friendly programmer interface.As a result, the research introduces a complete heterogeneous platform enhancedwith a hierarchical memory organization, which copes with its task bymeans of separating computation from communication, providing reconfigurableengines with computation and configuration data, and unification of heterogeneouscomputational devices using local storage buffers. It is distinguished from therelated solutions by distributed data-flow organization, specifically engineeredmechanisms to operate with data on local domains, particular communication infrastructurebased on Network-on-Chip, and thorough methods to prevent computationand communication stalls. In addition, a novel advanced technique to acceleratememory access was developed and implemented." @default.
• W165697058 created "2016-06-24" @default.
• W165697058 creator A5074314202 @default.
• W165697058 date "2008-04-08" @default.
• W165697058 modified "2023-09-27" @default.
• W165697058 title "Memory hierarchy and data communication in heterogeneous reconfigurable SoCs" @default.
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• W165697058 doi "https://doi.org/10.6092/unibo/amsdottorato/1127" @default.
• W165697058 hasPublicationYear "2008" @default.
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