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- W1660461258 abstract "The lock-up time of a PLL frequency synthesizer depends on each loop gain. In this paper, we pay attention to the gain of a programmable divider which is one of the important elements of PLL, and propose a new method for improving the gain of programmable dividers. In order to achieve the increase in the gain of the programmable divider, we have proposed a new PLL frequency synthesizer with multi-programmable divider by which the gain is increased even when the same reference frequency and the same division ratio as usual are used. In this paper we propose a simple PLL frequency synthesizer with an auxiliary programmable divider which is suitable for LSI implementation. It will be shown by theoretical considerations and experimental results that a higher speed lock-up time can be achieved." @default.
- W1660461258 created "2016-06-24" @default.
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- W1660461258 date "2003-01-20" @default.
- W1660461258 modified "2023-09-26" @default.
- W1660461258 title "PLL frequency synthesizer with an auxiliary programmable divider" @default.
- W1660461258 cites W2031703475 @default.
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- W1660461258 doi "https://doi.org/10.1109/iscas.1999.780800" @default.
- W1660461258 hasPublicationYear "2003" @default.
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