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- W1662540602 abstract "A novel high speed 0.25 /spl mu/m CMOS amplifier IP core is presented which use the complementary self-biasing differential amplifier technique. The proposed amplifier features a 418 MHz unity gain frequency and 375 V//spl mu/s slew rate with capacitive load 2pF. The output voltage of the proposed amplifier swings from Vgnd to Vdd and the static power less than 0.32 /spl mu/W. A Verilog-A behavioral model is presented for the amplifier IP core which contains the important non-idealities of the amplifier." @default.
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- W1662540602 date "2005-09-09" @default.
- W1662540602 modified "2023-09-25" @default.
- W1662540602 title "A high speed self-biased CMOS amplifier IP core" @default.
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- W1662540602 doi "https://doi.org/10.1109/iwvdvt.2005.1504450" @default.
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