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• W1666873040 abstract "AbstractTelegraphic noise is one of the most significant problems tha t arises when making sensitive measurements with lateral electrostaticdevices. In this paper we demonstrate that a wafer which had only produced devices with significant telegraph noise probl ems canbe made to produce ‘quiet’ devices if a thin insulator layer is placed between the gates and the GaAs/AlGaAs heterostructure. Aslow drift in the resulting devices is attributed to the trapping of charges within the specific insulator used. This char ge can bemanipulated, leading to strategies for stabilizing the device.Key words: Telegraph noise; Schottky barrier; Leakage currentPACS: 85.30.-z; 72.20.Jv; 72.70.+m; 73.23.-b1. IntroductionMany sensitive experiments involving lateral devices arenegatively affected by switching noise. These devices are usu-ally defined in the two dimensional electron gas (2DEG) withi nGaAs/AlGaAs heterostructures by means of electrostatic gates.Recently we showed that the origin of the noise lay in an in-terrupted leakage current from the gates used to define thedevice[1]. This has led to several strategies to mitigate thenoise. These include the use of ‘bias cooling’[1] which in-volves the application of a positive voltage to the gates dur-ing cooldown and ‘global gating’[2] which involves the appli-cation of a negativevoltage to a gate coveringthe whole device.Both of these techniques increase the effective tunnel barrier atthe metal-semiconductor interface and thus lower the leakagecurrent and hence the noise. In this paper, we show that byeliminating this interface altogether we are able to convert a’noisy’ wafer, i.e. one which has a history of generating onlynoisy devices, into one where the telegraph noise is eliminated.In addition to providing a route to making useful devices fromproblematic wafers, these experiments providefurther evidencefor our model for the origin of the noise.2. ExperimentWhile the origin of the telegraph noise lies in an interruptedleakage current, it is an empirical fact that some wafers aremuch more ‘noisy’ than others. For the experiments in this pa-per we used our ‘noisiest’ wafer which historically had onlyproduced devices with significant telegraph noise problems .For the global gate experiments, a large global gate was fab-ricated on top of three 40 nm layers of calixarene. This numberof layers was foundto be necessary to preventshorting betweengates due to pinholes in the calixarene. In the second ’floati nggate’ experiments, QPCs and quantum dots were fabricated ontop of a 40nm single layer of calixarene in separate fabricationruns. The layer structures are shown schematically in figure 1.A photograph of one of the QPCs on top of the calixarene, aswell as a global gate device are also shown. Calixarene is aclass of marcomolecules with relatively low molecular weightwhich is also a high resolution negative electron beam resist.Moreover, due to its robustness upon exposure and develop-ment, it can be employed as spacer dielectric layer between ourfabricated mesa and the fine gate structure used to form ourquantum dots. This layer was achieved by spinning calixarenedissolved in cholorbenzeneat 2000 rpm for 30 seconds and cur-ing at 180" @default.
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• W1666873040 date "2011-01-01" @default.
• W1666873040 modified "2023-09-27" @default.
• W1666873040 title "Silencing 'noisy' 2DEG wafers" @default.
• W1666873040 hasPublicationYear "2011" @default.
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