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- W1674310384 abstract "A simple but powerful parallel architecture based on the classical associative processor model, which allows bit-parallel computation and communication, is proposed. Complex operations such as multiplication execute in O(m) cycles, as opposed to O(m/sup 2/) for bit-serial machines. This permits very fast processing of floating-point data. A bit-parallel communication network that exploits associative data location independence is presented. It provides the system with a reconfiguration capability, which improves chip yield, as well as fault tolerance. The simplicity of the architecture lends itself to VLSI implementation and hence allows the construction of a bit-parallel, word-parallel, and massively parallel (P/sup 3/) computing system. >" @default.
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- W1674310384 date "2002-12-04" @default.
- W1674310384 modified "2023-09-25" @default.
- W1674310384 title "A bit-parallel, word-parallel, massively parallel associative processor for scientific computing" @default.
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- W1674310384 doi "https://doi.org/10.1109/fmpc.1990.89457" @default.
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