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- W169955824 abstract "We present a verification tool for the functional hardware description language SAFL. Model checking [JGP99] is a popular verification technique. Given a model of a finite state transition system, and a temporal logic specification, a model checker determines if the model satisfies the specification. Advantages of model checking over other verification techniques are that it is fully automatic, and can produce counter examples for false specifications. We have developed a model checker which uses the SAFL language as the modelling language. SAFL [MS00] is a functional hardware description language. As a result of this project, the same SAFL description can be used to describe a circuit and as a model for model checking. No separate model of the system is needed. It is hoped that this will make verification a regular part of the development process for SAFL programs. Just as a static type checker enforces safety properties for a programming language, we would like to see our model checker used to verify user-defined temporal properties before compiling SAFL programs to silicon. While limitations in model checking technology, (i.e., the state explosion problem), make achieving this goal unlikely for larger programs, techniques such as abstraction and a translation to an industrial-grade symbolic model checker, SMV, can be used to overcome them in many cases." @default.
- W169955824 created "2016-06-24" @default.
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- W169955824 date "2002-01-01" @default.
- W169955824 modified "2023-09-27" @default.
- W169955824 title "Model Checking for a Functional Hardware Description Language" @default.
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