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- W1727155093 abstract "This paper describes DLL (delay locked loop) with built-in DCC (duty cycle correction) capability using a newly proposed coded phase blending scheme. The proposed scheme dramatically improves the DCC range and also enhances the total DLL performance. The DLL has been designed and fabricated within 1G-bit DDR (double data rate) synchronous DRAM using 0.11 /spl mu/m process and the measurement data show that it has unlimited DCC range, faster turn-on speed and smaller jitter compared with our previous work (2001)." @default.
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- W1727155093 date "2004-03-02" @default.
- W1727155093 modified "2023-09-30" @default.
- W1727155093 title "Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM Application" @default.
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- W1727155093 doi "https://doi.org/10.1109/vlsic.2003.1221229" @default.
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