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- W1738647919 abstract "Delay insensitive circuits can solve several problems of VLSI designs. A synthesis system that automatically generates delay insensitive circuits from behavioral specifications has been developed by means of connection of dedicated standard cells. The electrical characterization of the standard cell set is presented, with emphasis on the new aspects introduced by this field of VLSI design. Complexity and speed parameters of each cell are reported. A first example of layout obtained by the system is present and evaluated. >" @default.
- W1738647919 created "2016-06-24" @default.
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- W1738647919 date "2003-01-02" @default.
- W1738647919 modified "2023-09-26" @default.
- W1738647919 title "A standard cell set for delay insensitive VLSI design" @default.
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- W1738647919 doi "https://doi.org/10.1109/asic.1992.270293" @default.
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