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- W1744634911 abstract "A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 /spl mu/m standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL." @default.
- W1744634911 created "2016-06-24" @default.
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- W1744634911 date "2003-11-04" @default.
- W1744634911 modified "2023-09-25" @default.
- W1744634911 title "A digitally controlled PLL for digital SOCs" @default.
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- W1744634911 doi "https://doi.org/10.1109/iscas.2003.1206308" @default.
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