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- W1745399674 abstract "In this paper, we extend our generalized methodology for designing a lower-error and area-time efficient 2's-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. The generalized methodology involving three steps results in several better error-compensation biases. These better error-compensation biases can be mapped to low-error fixed-width Booth multipliers suitable for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multipliers to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier." @default.
- W1745399674 created "2016-06-24" @default.
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- W1745399674 date "2004-12-23" @default.
- W1745399674 modified "2023-09-24" @default.
- W1745399674 title "A generalized methodology for low-error and area-time efficient fixed width booth multipliers" @default.
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- W1745399674 doi "https://doi.org/10.1109/mwscas.2004.1353884" @default.
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