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• W1749299286 abstract "This paper introduces a Built-In Self-Test (BIST) design methodology that can sequentially test large VLSI circuits with very high fault coverage. The proposed techniques, Circular Built-In Self-Test (CBIST) and CBIST with pseudo-partial scan (PP-SCAN), are modeled after the principles of the Circular Self-Test Path. The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It will be shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared to existing sequential test methods. >" @default.
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• W1749299286 date "2002-12-17" @default.
• W1749299286 modified "2023-09-26" @default.
• W1749299286 title "An efficient approach to low cost sequential circuit testing in a BIST environment" @default.
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• W1749299286 doi "https://doi.org/10.1109/asic.1994.404533" @default.
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