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• W1755376386 abstract "Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Single-Electron Transistor (SET) hybrid architectures, which combine the merits of both MOSFET and SET, promise to be a practical implementation for nanometer-scale circuit design. In this thesis, we design arithmetic circuits, including adders and multipliers, using SET/MOS hybrid architectures with the goal of reducing circuit area and power dissipation and improving circuit reliability. Thanks to the Coulomb blockade oscillation characteristic of SET, the design of SET/MOS hybrid adders becomes very simple, and requires only a few transistors by using the proposed schemes of multiple-valued logic (MVL), phase modulation, and frequency modulation. The phase and frequency modulation schemes are also further utilized for the design of multipliers with more discussions. Two types of SET/MOS hybrid multipliers are presented in this thesis. One is the binary tree multiplier which adopts conventional tree structures with multi-input counters (or compressors) implemented with the phase modulation scheme. Compared to conventional CMOS tree multipliers, the area and power dissipation of the proposed multiplier are reduced by half. The other is the frequency modulated multiplier following a novel design methodology where the information is processed in the frequency domain." @default.
• W1755376386 created "2016-06-24" @default.
• W1755376386 creator A5042162276 @default.
• W1755376386 date "2011-01-01" @default.
• W1755376386 modified "2023-09-27" @default.
• W1755376386 title "Hybrid MOS and Single-Electron Transistor Architectures towards Arithmetic Applications" @default.
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