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• W1760475501 abstract "Volumetric heat removal in high-performance 3D chip stacks can be performed by means of interlayer cooling. The heat is absorbed in water, which is pumped in the liquid phase into the cavities between the active layers. Individual through-silicon vias (TSV), which maintain the electrical communication between the layers, are embedded into silicon pins in the fluid cavity. Thousands of these TSVs are arranged on an equidistant grid. The mass transfer and consequently the heat removal strongly depend on the silicon pin-shape, which were assessed in this study. To predict the temperature field in a 3D chip-stack multi-scale, modeling approaches were proposed [6, 7, 8]. In a detailed subdomain model of the fluid cavity, the characteristic parameters, such as permeability and convective thermal resistance, are derived from a conjugate heat and masstransfer analysis. Thanks to the periodic arrangement of the pin fins only one unit cell with periodic hydrodynamic and thermal boundary conditions has to be modeled. Unfortunately, commercial computational fluid dynamics (CFD) solvers only provide periodic hydrodynamic boundary conditions. Therefore we demonstrate the implementation of periodic thermal boundary conditions for cases with imposed heat flux. At the fluid boundaries only convective energy transport is considered, whereas at the solid boundaries heat conduction is implemented. User Fortran routines are used to fetch and interpolate fluid temperature fields from the fluid outlet to the inlet, whereby the temperature gained within the unit cell is subtracted. The heat flux at the solid boundary is adjusted in a control loop with respect to the average fluid outlet to inlet temperature difference. These routines are called in the solver loop. Therefore the model only has to converge once. Compared with the classical approach with nonperiodic boundary conditions but multiple unit cells, a speed-up factor of 30 with a difference of at most 2 % could be obtained. Using this method, we computed the permeability and convective thermal resistance of circular, square, super-elliptic, and drop-shaped pins, with a pitch and height of 100 µm and a pressure gradient range of 1×106 to 1×107 Pa/m. The results are also compared with those obtained for parallel plates as well as with microchannel parameters derived from correlations. A pin-shape assessment was then performed for realistic fluid-cavity dimensions at a varying power map contrast. The “channel-walk-method” was used to define the maximum junction temperature for a given pressure drop and pin shape. For a peak-to-background heat-flux ratio of 1.5, the fluid temperature increase dominates the thermal budget. Therefore heat-transfer geometries with high permeability, such as parallel plates, perform best. At a higher heat-flux contrast of 5, the temperature increase caused by the convective thermal resistance at hotspot locations becomes significant. We could show that in this case drop-shaped pins, which offer a trade-off in terms of permeability and convective thermal resistance are superior." @default.
• W1760475501 created "2016-06-24" @default.
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• W1760475501 date "2010-11-15" @default.
• W1760475501 modified "2023-10-01" @default.
• W1760475501 title "Pin-shape assessment for interlayer-cooled chip stacks with periodic boundary condition modeling" @default.
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