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- W1761463679 abstract "Test patterns are used to prove the correct functionality and absence of manufacturing faults after producing a chip. The automatic generation of those test patterns for sequential circuits is harder than NP-complete problems and therefore an interesting algorithm to parallelize.In this paper we describe a parallel approach for automatic test pattern generation (ATPG) using PVM with optimal load balancing. The main advantage over existing approaches is a dynamic solution for partitioning the fault list and the search tree resulting in a very small overhead for communication without the need of any broadcasts and an optimal load balancing without idle times for the test pattern generators." @default.
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- W1761463679 date "1996-01-01" @default.
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- W1761463679 title "Automatic test pattern generation with optimal load balancing" @default.
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- W1761463679 doi "https://doi.org/10.1007/3540617795_26" @default.
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