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- W1774830880 abstract "A synthesis method and a CAD program to provide racefree asynchronous CMOS circuits that are independent of the internal and output delays are presented. The method minimizes the number of transitions between stable states and the number of gates, providing new cells for fast and low-power integrated circuits. Without any additional cost, the circuit will present neither critical races nor hazards (no race exists between any two variables), and the circuit is suitable for integration of low-power or very fast applications. >" @default.
- W1774830880 created "2016-06-24" @default.
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- W1774830880 date "2002-12-04" @default.
- W1774830880 modified "2023-09-25" @default.
- W1774830880 title "Logic synthesis of asynchronous circuits" @default.
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- W1774830880 doi "https://doi.org/10.1109/cicc.1990.124831" @default.
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