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- W1775955075 abstract "A novel 32-bit adder has been designed using a Conditional Sum Adder (CSA) architecture and CPL-like logic implementation. The new implementation outperforms several architectures such as CLA, CS and Manchester which use the CMOS circuit styles (CPL, DPL, TG, static-conventional) in terms of power and speed. This is verified for a range of power supply voltage from 3.3 V down to 1 V. The comparison is carried out for two designs, minimum size and optimized speed." @default.
- W1775955075 created "2016-06-24" @default.
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- W1775955075 date "2002-11-19" @default.
- W1775955075 modified "2023-09-24" @default.
- W1775955075 title "Circuit/architecture for low-power high-performance 32-bit adder" @default.
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- W1775955075 doi "https://doi.org/10.1109/glsv.1995.516028" @default.
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