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- W1776215724 abstract "We describe the application of model checking using FormalCheck to an industrial RTL design. It was used as a complement to classical simulation on portions of the chip that involved complex interactions and were difficult to verify by simulation. We also identify certain circuit structures that for a certain type of queries lend themselves to manual model reductions which were not detected by the automatic reduction algorithm. These reductions were instrumental in allowing us to complete the formal verification of the design and to detect two design errors that would have been hard to detect by simulation. We also provide a technique to estimate the length of a random simulation needed to detect a particular design error with a given probability; this length can be used as a measure of its difficulty." @default.
- W1776215724 created "2016-06-24" @default.
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- W1776215724 date "1999-01-01" @default.
- W1776215724 modified "2023-10-01" @default.
- W1776215724 title "Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors" @default.
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- W1776215724 doi "https://doi.org/10.1007/3-540-48153-2_10" @default.
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