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- W1777852485 abstract "An incremental synthesis method which enables ASIC designers to incrementally modify their register-transfer-level (RTL) behavior descriptions is described. This synthesis method synthesizes and optimizes only RTL behaviors which have been modified. An incremental synthesis approach reduces the overall synthesis time when an incremental modification has been performed. This synthesis method allows ASIC designers to control the design space exploration more closely. >" @default.
- W1777852485 created "2016-06-24" @default.
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- W1777852485 date "2003-01-02" @default.
- W1777852485 modified "2023-09-25" @default.
- W1777852485 title "An incremental synthesis method for ASIC design" @default.
- W1777852485 cites W2165601350 @default.
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- W1777852485 doi "https://doi.org/10.1109/asic.1992.270287" @default.
- W1777852485 hasPublicationYear "2003" @default.
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