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• W1781170684 abstract "This paper presents two basic high-efficiency low-power approaches for driving multi-clock chips and systems from only one external clock source. In the first approach a high-frequency crystal oscillator with reduced power-consumption is used to generate all the system frequencies. For the second approach, a low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, one-cycle frequency lock-in time and very high frequency multiplication factor is presented." @default.
• W1781170684 created "2016-06-24" @default.
• W1781170684 creator A5047489067 @default.
• W1781170684 date "2002-12-24" @default.
• W1781170684 modified "2023-09-30" @default.
• W1781170684 title "High-efficiency low-power one-clock solutions for multi-clock chips and systems" @default.
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• W1781170684 doi "https://doi.org/10.1109/amicd.1996.569385" @default.
• W1781170684 hasPublicationYear "2002" @default.
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