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- W17841638 abstract "i List of Tables v List of Figures vi Chapter 1: Introduction 1 1.1 Motivation 1 1.1.1 Shrinking Feature Size 1 1.1.2 Application to Architecture 3 1.2 Summary of Paper 4 1.3 Paper Organization 6 Chapter 2: State of the Art 8 Chapter 3: Probabilistic Modeling for Reliability 11 3.1 Gate Error Estimation 11 3.1.1 Errors Due to Physical Attributes 11 3.1.2 Error at the Output of a Gate 12 3.1.3 Examples 13 3.2 DTMCs 18" @default.
- W17841638 created "2016-06-24" @default.
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- W17841638 date "2000-01-01" @default.
- W17841638 modified "2023-10-14" @default.
- W17841638 title "Probabilistic Analysis for Reliable Logic Circuits" @default.
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- W17841638 doi "https://doi.org/10.15760/etd.1859" @default.
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